STEP 8: Post-Route (Signoff) STA
This step explains the final and most critical stage of Static Timing Analysis. Post-Route STA, also called Signoff STA, is performed after detailed routing and parasitic extraction are complete. The results from this stage determine whether the design is ready for tape-out. Timing signoff means that the design is verified to operate correctly under all specified conditions on silicon.
What is Post-Route STA
Post-Route STA is timing analysis performed using the fully routed design with accurate parasitic information. At this stage, both data paths and clock paths are physically realized. All interconnect resistance and capacitance values are extracted from the layout, providing a realistic model of signal behavior.
This stage represents the closest approximation of actual silicon behavior and therefore carries the highest level of confidence.
Accurate RC Extracted Timing
After routing, parasitic extraction tools calculate precise resistance and capacitance values for every net in the design. These extracted RC values include wire resistance, ground capacitance, coupling capacitance, and via effects.
Static Timing Analysis uses this extracted RC data to compute accurate propagation delays and signal transitions. Compared to pre-route estimates, extracted timing reflects the real physical environment of the chip.
Crosstalk Delay and Noise
Crosstalk occurs due to coupling capacitance between neighboring nets. When a signal on one net switches, it can affect the voltage and timing of an adjacent net.
Crosstalk delay refers to the increase or decrease in signal delay caused by neighboring switching activity. Crosstalk noise refers to unwanted voltage fluctuations induced on a net due to adjacent transitions.
These effects can cause additional setup or hold violations and must be included in signoff analysis.
Signal Integrity Aware STA
Signal Integrity aware STA accounts for the impact of crosstalk, noise, and waveform degradation on timing. It models how simultaneous switching of nearby nets affects delay and signal quality.
SI-aware STA ensures that timing margins remain valid even under worst-case coupling scenarios. This analysis is essential in deep submicron technologies where interconnect density is high.
Setup Timing Checks
Setup checks verify that data arrives at capturing elements before the required clock edge minus setup time. At signoff, setup checks are performed using worst-case delay conditions, including extracted RC and crosstalk effects.
Passing setup timing at this stage indicates that the design can operate at the target frequency under slow conditions.
Hold Timing Checks
Hold checks verify that data does not arrive too early at capturing elements. At signoff, hold checks are performed using best-case delay conditions with extracted parasitics.
Passing hold timing ensures that fast paths and clock skew effects do not cause functional failures.
Recovery and Removal Checks
Recovery and removal checks apply to asynchronous control signals such as reset or set. Recovery time is the minimum time the control signal must be stable before the clock edge. Removal time is the minimum time the control signal must remain stable after the clock edge.
These checks ensure that asynchronous controls do not interfere with normal clocked operation.
Pulse Width Checks
Pulse width checks ensure that clock pulses remain high or low for a sufficient duration. Very narrow pulses can prevent correct operation of sequential elements.
Post-route STA verifies that clock and control signals meet minimum pulse width requirements under all conditions.
Clock Gating Checks
Clock gating checks ensure that clock gating logic does not create glitches or violate timing requirements. These checks verify the enable signal timing relative to the clock to prevent unintended clock pulses.
Correct clock gating is essential for both functionality and power optimization.
What Timing Signoff Means
Timing signoff means that all timing checks have passed across all required operating conditions, modes, and corners using the most accurate timing models available. It indicates that the design meets its timing specifications and is safe to manufacture.
Signoff STA is a mandatory requirement before tape-out and represents the final confirmation of timing correctness.
Goal of Post-Route STA
The goal of this step is to understand that timing signoff is not just another analysis step but the final approval of timing correctness. By understanding extracted RC, crosstalk, signal integrity, and comprehensive timing checks, one can clearly understand what timing signoff truly means in real-world digital design flows.