STEP 7: Interconnect and Parasitics
This step explains how physical interconnect affects timing in digital designs. As designs move from logical implementation to physical realization, wires become a dominant factor in timing behavior. Understanding interconnect and parasitics is essential to explain why timing that appears clean before routing can change significantly after routing.
Resistance
Resistance is the opposition offered by an interconnect to the flow of electrical current. In integrated circuits, resistance arises from the finite conductivity of metal wires and vias. Longer wires, narrower wires, and multiple vias increase resistance.
Resistance causes voltage drop along the wire and slows down signal transitions. In timing analysis, higher resistance increases signal delay because it takes more time to charge or discharge the load capacitance at the receiving end.
Capacitance
Capacitance is the ability of a structure to store electrical charge. In interconnects, capacitance arises between a wire and the substrate, as well as between neighboring wires.
Capacitance determines how much charge is required to change the voltage on a net. Higher capacitance means more charge is needed, which slows down signal transitions. Capacitance directly affects both delay and signal integrity.
Delay Impact of Long Nets
Long nets have higher resistance and higher capacitance. As net length increases, the combined resistance and capacitance increase, resulting in larger propagation delay.
In modern technologies, interconnect delay often dominates gate delay. This means that even if the logic is optimized, long routing paths can still cause timing violations. Long nets are a common cause of setup timing failures after routing.
Why Routing Changes Timing
Before routing, interconnect delays are estimated using simple models. After routing, actual wire lengths, metal layers, spacing, and via counts are known. This results in more accurate and often larger delay values.
Routing also introduces coupling capacitance between adjacent nets, which further affects delay. Because of these physical realities, timing results after routing can differ significantly from pre-route estimates.
Pre-Route Versus Post-Route Differences
Pre-route timing analysis uses estimated interconnect delays based on fanout or rough wire models. These estimates lack accuracy and do not capture detailed physical effects.
Post-route timing analysis uses extracted parasitics from the actual routed design. This includes accurate resistance and capacitance values for every net. As a result, post-route timing is much closer to silicon behavior.
SPEF and Extracted RC Concept
Standard Parasitic Exchange Format is a file format used to describe extracted parasitic information. SPEF files contain resistance and capacitance values for nets based on the routed layout.
Extracted RC refers to the resistance and capacitance values obtained from physical extraction tools. STA tools use this extracted RC data to calculate accurate propagation delays.
Using extracted RC ensures that timing analysis reflects real physical behavior rather than estimates.
Goal of Interconnect and Parasitics Understanding
The goal of this step is to understand that wires are not ideal and that their physical properties significantly impact timing. By understanding resistance, capacitance, and extracted parasitics, one can explain why timing changes after routing and why post-route STA is essential for reliable design signoff.