STEP 3: Pre-Layout STA (Pre-CTS)
This step explains Static Timing Analysis as it is performed before any physical implementation of the design. Pre-Layout STA is the first stage where STA tools are actively used. The purpose of this stage is not final signoff but to verify that the design is logically and timing-wise correct before clock tree synthesis and placement begin.
What is Pre-Layout STA
Pre-Layout STA is the timing analysis performed on a synthesized gate-level netlist without any physical placement or routing information. At this stage, the design exists only in logical form. There is no knowledge of actual wire lengths, parasitics, or clock tree delays.
Static Timing Analysis at this stage uses estimated delays and ideal clock assumptions to evaluate whether the design can theoretically meet its timing requirements.
Ideal Clocks
In Pre-Layout STA, clocks are modeled as ideal. This means that the clock arrives at all sequential elements at the same time. There is no clock insertion delay, no clock skew, and no clock jitter considered.
The clock is treated as a perfect reference signal. This assumption simplifies analysis and allows designers to focus on data path timing rather than clock distribution effects. Because of this, setup timing is the primary focus during Pre-Layout STA.
Wireload and Estimated RC
Since placement and routing have not yet occurred, actual interconnect resistance and capacitance values are unknown. To approximate interconnect delay, Pre-Layout STA uses wireload models or early estimated RC values.
Wireload models estimate wire delay based on factors such as fanout and design size. Estimated RC models use rough assumptions about resistance and capacitance to predict interconnect delay. These estimates are not accurate but provide a reasonable approximation of how wires will affect timing later.
The purpose of estimated RC is to identify potential long or slow paths early in the design flow.
Timing Libraries
Timing libraries, typically provided in Liberty format (.lib), contain detailed timing information for standard cells. These libraries include cell delays, setup and hold times, clock-to-Q delays, and transition characteristics under various operating conditions.
In Pre-Layout STA, the STA tool uses timing libraries to calculate gate delays based on estimated input transitions and output loads. The accuracy of Pre-Layout STA depends heavily on the quality and correctness of these libraries.
Reading Synthesis Timing Reports
One of the most important practical skills at this stage is learning how to read synthesis timing reports. These reports summarize the timing health of the design after synthesis.
A timing report typically lists the worst timing paths, shows how delays accumulate along the path, and provides slack values. Understanding these reports helps identify which parts of the design are limiting performance.
Worst Negative Slack
Worst Negative Slack represents the most severe timing violation in the design. It is the smallest slack value among all analyzed paths. A negative value indicates that at least one path fails timing.
Worst Negative Slack is often used as a quick indicator of whether the design meets timing or not at this stage.
Total Negative Slack
Total Negative Slack is the sum of all negative slack values across all failing paths. It provides a measure of how widespread timing violations are in the design.
A small Worst Negative Slack with a large Total Negative Slack indicates many failing paths. A large Worst Negative Slack with a small Total Negative Slack indicates a few severe failing paths.
Critical Path
The critical path is the timing path with the worst slack in the design. It determines the maximum operating frequency of the design at that stage.
In Pre-Layout STA, identifying the critical path helps designers understand which logic structures or functions are most timing-sensitive and may require optimization.
Focus on Setup Timing
During Pre-Layout STA, the primary focus is on setup timing. Because clocks are ideal and there is no skew, hold violations are either rare or not meaningful at this stage.
Setup timing failures indicate that the data path delay is too large to meet the target clock period. These failures are typically addressed by optimizing logic, reducing logic depth, or improving synthesis constraints.
Path Grouping
Path grouping is the process of categorizing timing paths based on their start and end points, such as register-to-register, input-to-register, and register-to-output paths.
Path grouping helps in analyzing timing more systematically and allows designers to apply different constraints or optimization strategies to different types of paths.
Constraint Correctness
Correct timing constraints are critical for meaningful Pre-Layout STA results. Constraints define how the STA tool interprets clock behavior, input timing, output timing, false paths, and multicycle paths.
Incorrect or missing constraints can lead to misleading timing reports, either hiding real problems or showing false violations. Verifying constraint correctness is one of the key objectives of Pre-Layout STA.
Goal of Pre-Layout STA
The goal of Pre-Layout STA is to ensure that the design is timing-correct by intent before physical implementation begins. This stage helps identify logical timing issues, constraint problems, and fundamentally slow paths early in the flow, reducing the risk of severe timing failures during clock tree synthesis and routing.
Understanding Pre-Layout STA enables one to clearly see why timing can fail even before placement and routing and prepares the foundation for more detailed timing analysis in later stages.