STEP 5: Clock Tree Concepts (Before CTS STA)
This step explains how clocks behave as real signals inside a chip and how their behavior affects timing analysis. Before clock tree synthesis, clocks are often treated as ideal, but understanding real clock concepts is essential to correctly interpret timing behavior once clock delays are introduced. Clock tree concepts explain why the same data path can pass setup timing but fail hold timing, or vice versa.
Clock Latency
Clock latency is the amount of time taken by the clock signal to travel from its source to a clock pin of a sequential element. The clock source can be a PLL, clock generator, or external clock input.
Clock latency includes delays introduced by clock buffers, inverters, clock gating cells, and interconnect. It determines when a flip-flop actually sees the clock edge, not when the clock is generated.
In timing analysis, clock latency shifts the effective launch and capture times of data. Larger clock latency means the clock edge reaches the flip-flop later.
Source Latency
Source latency is the portion of clock latency that occurs from the clock source to the defined clock root. It represents delay outside or at the boundary of the design.
Source latency is often used to model delays from an external clock source or PLL to the point where the clock enters the design. This latency affects both launch and capture clocks in the same way if they share the same source.
Network Latency
Network latency is the portion of clock latency that occurs within the clock distribution network inside the design. It includes delays through clock buffers, clock routing, and clock tree structures.
Network latency can differ between different flip-flops. Differences in network latency are a primary cause of clock skew.
Clock Skew
Clock skew is the difference in clock arrival time between two sequential elements, typically a launching flip-flop and a capturing flip-flop.
If the clock arrives at the capturing flip-flop later than at the launching flip-flop, the skew is positive. If the clock arrives earlier at the capturing flip-flop, the skew is negative.
Clock skew arises due to unequal clock path delays and is unavoidable in real designs.
Positive Clock Skew
Positive clock skew means that the capture clock edge arrives later than the launch clock edge. This effectively increases the available time for data to travel between the two flip-flops.
Positive skew generally helps setup timing because it relaxes the setup requirement. However, it can make hold timing worse by allowing data to arrive too early relative to the delayed capture clock.
Negative Clock Skew
Negative clock skew means that the capture clock edge arrives earlier than the launch clock edge. This reduces the available time for data to propagate.
Negative skew generally hurts setup timing because it tightens the setup requirement. However, it can help hold timing by reducing the chance of data arriving too early.
Clock Uncertainty
Clock uncertainty represents variations and inaccuracies in clock timing. It accounts for factors such as clock jitter, on-chip variation, and modeling uncertainty.
Clock uncertainty reduces the effective timing margin. In setup analysis, uncertainty reduces the available time for data to arrive. In hold analysis, uncertainty increases the required minimum delay.
Including clock uncertainty ensures that the design remains robust under real operating variations.
How Skew Affects Setup Timing
Setup timing depends on the relative difference between the launch and capture clock edges. Positive skew increases the time window available for data propagation, making setup easier to meet. Negative skew reduces this window, making setup timing more difficult.
Understanding this relationship allows designers to predict whether a given skew condition will improve or degrade setup timing.
How Skew Affects Hold Timing
Hold timing checks whether data remains stable immediately after the launch clock edge. Positive skew delays the capture clock, which can cause the capturing flip-flop to see new data too soon, increasing the risk of hold violations. Negative skew moves the capture clock earlier, which can help prevent hold violations.
This opposite impact of skew on setup and hold timing is one of the most important concepts in STA.
Goal of Clock Tree Concepts
The goal of this step is to develop the ability to reason about clock behavior without relying solely on tool reports. By understanding clock latency, skew, uncertainty, and the distinction between source and network latency, one can predict whether clock skew will help or hurt timing and understand why timing behavior changes after clock tree synthesis.