STEP 6: Post-CTS STA (Clock-Aware STA)
This step explains Static Timing Analysis after Clock Tree Synthesis has been completed. Post-CTS STA is the stage where clocks are no longer ideal and real clock delays are introduced into timing analysis. This stage is critical because it reveals timing issues that cannot be seen in Pre-Layout STA, especially hold violations.
What is Post-CTS STA
Post-CTS STA is timing analysis performed after the clock tree has been synthesized and inserted into the design. At this stage, the clock distribution network exists logically, and clock insertion delays are known with reasonable accuracy. Although detailed routing may not yet be complete, the clock network delay information is realistic enough to significantly affect timing.
The primary purpose of Post-CTS STA is to analyze timing with clock-aware behavior and to fix clock-related timing issues before routing.
Real Clock Insertion Delays
After CTS, each flip-flop receives the clock through a network of buffers and interconnect. This introduces real clock insertion delays, which represent the time taken for the clock signal to travel from the clock source to each flip-flop.
Unlike Pre-Layout STA, where clocks arrive simultaneously at all flip-flops, Post-CTS STA accounts for different clock arrival times at different sequential elements. These differences directly influence setup and hold timing calculations.
Hold Violations After CTS
Hold violations often appear or increase significantly after CTS. This happens because clock skew is introduced by the clock tree. When the capture clock arrives later than the launch clock, data can reach the capturing flip-flop too early, causing a hold violation.
Before CTS, ideal clocks hide these effects. After CTS, even very short data paths may fail hold timing due to clock skew and reduced effective hold margins.
Setup Versus Hold Trade-Off
Post-CTS STA highlights the fundamental trade-off between setup and hold timing. Actions that improve setup timing can worsen hold timing, and actions that fix hold timing can degrade setup timing.
For example, adding buffers to a data path increases delay, which helps fix hold violations but can reduce setup margin. Similarly, clock skew that helps setup timing may cause hold violations. Understanding this trade-off is essential for effective timing closure.
Focus on Hold Fixing Strategies
The main focus of Post-CTS STA is hold fixing. Since setup issues are largely addressed during synthesis and Pre-Layout STA, Post-CTS efforts concentrate on ensuring that data paths are not too fast.
Hold fixing is done carefully to avoid introducing new setup violations.
Buffer Insertion Logic
One of the most common techniques for fixing hold violations is buffer insertion in the data path. Buffers increase the minimum delay of the data path, ensuring that data does not arrive too early at the capturing flip-flop.
Buffers are inserted in non-critical locations to minimize impact on setup timing. The goal is to increase the minimum delay without significantly affecting the maximum delay.
Path-Based Analysis Versus Graph-Based Analysis
Graph-based analysis evaluates timing using worst-case assumptions across the timing graph. It is fast but pessimistic.
Path-based analysis evaluates complete timing paths individually and considers correlations between delays. It provides more accurate results but requires more computation.
In Post-CTS STA, path-based analysis is often used to accurately evaluate hold-critical paths and to avoid unnecessary or excessive hold fixes.
Why Hold is Mainly Fixed Post-CTS
Hold violations are primarily caused by clock skew and fast data paths. These conditions are not fully visible until real clock insertion delays are known, which occurs after CTS.
Because of this, hold timing is intentionally left for Post-CTS STA, where clock behavior is realistic. Fixing hold too early can lead to over-constraining the design and unnecessary area or power overhead.
Goal of Post-CTS STA
The goal of Post-CTS STA is to ensure that the design is robust against clock skew and real clock delays. By understanding real clock insertion delays, setup versus hold trade-offs, and hold fixing strategies, one can understand why hold timing is mainly addressed after clock tree synthesis and how clock-aware STA enables reliable timing closure.